1. Field of the Invention
The present invention relates to semiconductor memory devices, and to circuits for generating word line control signals in semiconductor memory devices.
2. Description of the Related Art
Semiconductor memory devices perform read operation or write operations in response to a voltage signal of a word line. FIG. 1 is a circuit diagram showing a prior art sub-word line driver (SWD) for a DRAM (Dynamic Random Access Memory). Such a circuit is disclosed in Korean laid-open publication No. 2002-0033883.
Referring to FIG. 1, the sub-word line driver circuit includes 4 NMOS transistors NM1 through NM4. The sub-word line driver of FIG. 1 drives the corresponding word lines in response to the signals WEI, PXI, PXIB generated by a circuit for generating word line control signal (not shown). When the word line enable signal WEI is logic “high”, the voltage of the boost node BN is VPP−Vth. Vth represents a threshold voltage of an NMOS transistor. Then, when the word-line boosting signal PXI turns to the logic high state, the voltage of the boost node BN is boosted to 2Vpp−Vth.
The self-boosting operation is performed by capacitance coupling which exists due to the parasitic capacitor between the gate and the drain of the NMOS transistor MN2. Therefore, the voltage of the word line WL reaches the boost voltage level VPP and the memory cells connected to the word line WL operates safely because the word-line boosting signal PXI supplies a sufficient current to the word line WL through the NMOS transistor MN2. The high level of the signals WEI, PXI, and PXIB is VPP. When the word line is discharged and the voltage of the word line is turned to a logic low state.
FIG. 2 shows a timing diagram of signals in the circuit in FIG. 1. The time interval BM between the point at which the word line enable signal WEI turns to a logic high and the point at which the word-line boosting signal PXI turns to a logic high is called self-boosting margin.
FIG. 3 is a timing diagram showing the self-boosting margin of the sub-word line driver of FIG. 1 when the DRAM operates in a normal active mode and in a refresh mode.
Referring to FIG. 3, the self-boosting margin decreases when a DRAM operates in the refresh mode, unlike that in the normal active mode. When a DRAM operates in the refresh mode, the word line enable signal WEI is delayed for the time tdw compared with when the DRAM operates in the normal active mode. Referring further to FIG. 3, it can be noted that the self-boosting margin BMR in the refresh mode is decreased compared with the self-boosting margin BMN in the normal active mode.
The level of the supply voltage used when the reliability of the semiconductor memory device is tested may be higher than the supply voltage used when the semiconductor memory device operates normally. Therefore, the delay time in the acceleration condition for testing the reliability may be decreased compared with a delay time in the normal condition, and the self-boosting margin in the acceleration condition for testing the reliability may be decreased compared with a self-boosting margin in the normal condition.